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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT16543 16-BIT LATCHED TRANSCEIVERS
PI74LPT16543
1098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Fast CMOS 16-Bit Latched Transceivers
Product Features
* Compatible with LCXTM and LVTTM families of products * Supports 5V Tolerant Mixed Signal Mode Operation - Input can be 3V or 5V - Output can be 3V or connected to 5V bus * Advanced Low Power CMOS Operation * Excellent output drive capability: Balanced drives (24 mA sink and source) * Pin compatible with industry standard double-density pinouts * Low ground bounce outputs * Hysteresis on all inputs * Industrial operating temperature range: -40C to +85C * Multiple center pins and distributed Vcc/GND pins minimize switching noise * Packages available: - 56-pin 240 mil wide plastic TSSOP (A) - 56-pin 300 mil wide plastic SSOP (V)
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Product Description
Pericom Semiconductor's PI74LPT series of logic circuits are produced in the Company's advanced 0.6 micron CMOS technology, achieving industry leading speed grades. The PI74LPT16543 is 16-bit latched transceivers organized with two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the Ato-B Enable (xCEAB) input must be LOW in order to enter data from xAx or to take data from xBx, as indicated in the Truth Table. With xCEAB LOW, a LOW signal makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the xLEAB signal puts the A latches in the storage mode and their outputs no longer change the A inputs. With xCEAB and xOEAB both LOW, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses the xCEAB, xLEAB, and xOEAB inputs. The PI74LPT16543 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3/5.0V system.
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Logic Block Diagram
1OEBA 2OEBA
9 10
1CEBA
2CEBA
1LEBA 1OEAB
2LEBA 2OEAB
11
C
2B0
1CEAB
2CEAB
1LEAB 1A0
C
1B0
2LEAB 2A0
12 13 14 15
D C C
D
D
D
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
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PS2072A 01/16/97
Product Pin Description
Pin Name xOEAB xOEBA xCEAB xCEBA xLEAB xLEBA xAx xBx GND VCC Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or B-to-A 3-State Outputs Ground Power
Product Pin Configuration
1OEAB 1LEAB 1CEAB
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT16543 16-BIT LATCHED TRANSCEIVERS
Truth Table(1)
Inputs
XCEAB XLEAB XOEAB
Latch Status
XAX TO XBX
Output Buffers
XBX
H X X L L
X H X L H
X X H L L
Storing High Z Storing X X High Z Transparent Current A Inputs Storing Previous* A Inputs
NOTES: 1. *Before xLEAB LOW-to-HIGH Transistion H = High Voltage Level L = Low Voltage Level X = Don't Care or Irrelevant Z = High Impedance 2. A-to-B data flow shown. B-to-A flow control is the same, except using xCEBA, xLEBA, and xOEBA.
GND
1A0 1A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 56-PIN 46 V56 45 A56 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1LEBA 1CEBA
GND
1B0 1B1
VCC
1A2 1A3 1A4 GND 1A5 1A6 1A7 2A0 2A1 2A2 GND 2A3 2A4 2A5
VCC
1B2 1B3 1B4 GND 1B5 1B6 1B7 2B0 2B1 2B2 GND 2B3 2B4 2B5
VCC
2A6 2A7
VCC
2B6 2B7
GND
2CEAB 2LEAB 2OEAB
GND
2CEBA 2LEBA 2OEBA
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PS2072A 01/16/97
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT16543 16-BIT LATCHED TRANSCEIVERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................. -55C to +125C Ambient Temperature with Power Applied ............................ -40C to +85C Supply Voltage to Ground Potential (Inputs & Vcc Only) ...... -0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. -0.5V to +7.0V DC Input Voltage .................................................................... -0.5V to +7.0V DC Output Current .............................................................................. 120 mA Power Dissipation .................................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C, VCC = 2.7V to 3.6V)
Parameters VIH VIL IIH IIL IOZH IOZL VIK IODH IODL VOH Description Input HIGH Voltage (Input pins) Input HIGH Voltage (I/O pins) Input LOW Voltage (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Min. 2.2 2.0 -0.5 Typ(2) -- -- -- -- -- -- -- -- -- -0.7 -60 90 -- 3.0 3.0 -- -- 0.2 0.3 -85 -- 150 Max. 5.5 5.5 0.8 1 1 1 1 1 1 -1.2 -110 200 -- -- -- -- 0.2 0.4 0.5 -240 100 -- Units V V V A A A A A A V mA mA V V V V V V mA A mV
VOL
Output LOW Voltage
IOS IOFF VH
Short Circuit Current(4) Power Down Disable Input Hysteresis
VCC = Max. VIN = 5.5V -- VCC = Max. VIN = VCC -- VCC = Max. VIN = GND -- VCC = Max. VIN = GND -- VCC = Max. VOUT = 5.5V -- VCC = Max. VOUT = GND -- VCC = Min., IIN = -18 mA -- VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) -36 (3) VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V 50 VCC = Min. IOH = -0.1 mA Vcc-0.2 VIN = VIH or VIL IOH = -3 mA 2.4 VCC = 3.0V, IOH = -8 mA 2.4(5) VIN = VIH or VIL IOH = -24 mA 2.0 VCC = Min. IOL = 0.1 mA -- VIN = VIH or VIL IOL = 16 mA -- IOL = 24 mA -- VCC = Max.(3), VOUT = GND -60 VCC = 0V, VIN or VOUT 4.5V -- --
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC - 0.6V at rated current.
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PS2072A 01/16/97
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT16543 16-BIT LATCHED TRANSCEIVERS
Power Supply Characteristics
Parameters Description ICC ICC ICCD Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply(4) Test Conditions(1) VCC = Max. VCC = Max. VCC = Max., Outputs Open XOE = GND One Bit Toggling 50% Duty Cycle VCC = Max., Outputs Open fI = 10 MHZ 50% Duty Cycle XOE = GND One Bit Toggling VCC = Max., Outputs Open fI = 2.5 MHZ 50% Duty Cycle XOE = GND 16 Bits Toggling VIN = GND or VCC VIN = VCC - 0.6V(3) VIN = VCC VIN = GND Min. Typ(2) 0.1 2.0 50 Max. 10 30 75 Units A A A/ MHz
IC
Total Power Supply Current(6)
VIN = VCC - 0.6V VIN = GND
0.6
2.3
mA
VIN = VCC - 0.6V VIN = GND
2.1
4.7(5)
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz.
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PS2072A 01/16/97
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT16543 16-BIT LATCHED TRANSCEIVERS
Switching Characteristics over Operating Range(1)
LPT16543 Com. LPT16543A Com. Max Min(3) Max Min(3) LPT16543C Com. Max Unit
1 2
ns
Parameters tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o)
Description Propagation Delay Transparent Mode xAx to xBx or xBx to xAx Propagation Delay xLEBA to xAx, xLEAB to xBx Output Enable Time xOEBA or xOEAB to xAx or xBx Output Disable Time(4) xOEBA or xOEAB to xAx or xBx Setup Time HIGH or LOW xAx or xBx to xLEAB or xLEBA Hold Time HIGH or LOW xAx or xBx to xLEAB or xLEBA xLEAB or xLEBA Pulse Width LOW Output Skew(5)
Conditions(2) CL = 50 pF RL = 500
Min(3)
2.5
8.5
2.5
6.5
2.5
5.3
3
2.5 2.0 2.0 3.0 2.0 5.0 -- 12.5 12.0 9.0 -- -- -- 0.5 2.5 2.0 2.0 2.0 2.0 5.0 -- 8.0 9.0 7.5 -- -- -- 0.5 2.5 2.0 2.0 2.0 2.0 5.0 -- 7.0 8.0 6.5 -- -- -- 0.5 ns ns ns ns ns ns ns
4 5 6 7 8 9 10
Notes: 1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V 0.3V, normal range. For Vcc = 2.7V, extended range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and wave forms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. This parameter is guaranteed but not production tested. 5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Capacitance (TA = 25C, f = 1 MHz)
Parameters(1) CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Typ 4.5 5.5 Max. 6 8 Units pF pF
11 12 13 14 15
Note: 1. This parameter is determined by device characterization but is not production tested.
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PS2072A 01/16/97

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